Note: this project finished in 1994
We propose a performance evaluation scheme for parallel VHDL simulation. This scheme provides accurate information about the performance of various parallel event driven simulation algorithms.
A compiler is used to translate the VHDL source into C++ which is linked with the parallel simulation algorithm and executed using a parallel architecture simulator. Because of the flexibility of the simulation tools, we can exchange simulation algorithms very quickly and can use a wide variety of network types and topologies.
Thanks to a careful design of the tools, they can be used for other simulation problems with only minimal changes.